1. Field of the Invention
The present invention relates to a system for processing semiconductor wafers, and more particularly to a semiconductor wafer processing system having a multi-layered arrangement of wafer processing units included in a spinner to carry out photoresist coating and developing processes for the formation of micro patterns on semiconductor wafers, thereby enabling an easy increase in those processing units coping with an introduction of new processes without increasing the occupying space of the processing units, while having a configuration capable of achieving accurate wafer feeding and loading operations, and minimizing the consumption of a chemical solvent coated over wafers.
2. Description of the Prior Art
As well known, a photo-lithography process is an important process in the processing of semiconductor wafers. Such a photo-lithography process is carried out using an integrated coating and developing installation which performs a coating process for coating a photoresist solution over a wafer, a baking process for the coated photoresist, and a developing process for the baked photoresist. The integrated coating and developing installation is connected with a stepper in an in-line manner via an interface. Such an integrated coating and developing installation is an important device for the formation of micro patterns on wafers, namely, the fabrication of highly integrated semiconductor devices.
Meanwhile, a variety of new techniques requiring an introduction of new processes have also been proposed for the fabrication of semiconductor devices with a super integration degree. Furthermore, the recent trend to use wafers with an increased size has resulted in an increase in the scale of wafer processing installations and a complexity in the arrangement of wafer processing installations.
FIGS. 1a and 1b are a perspective view and a plan view respectively illustrating a general spinner. As shown in FIGS. 1a and 1b, the spinner includes an indexer 1 for carrying out wafer loading and unloading operations, a feeding robot 2 for feeding a loaded wafer to processing units, respectively, a spin coater 3 for coating a photoresist solution over the wafer, and a spin developer 4 for developing the wafer subjected to a light exposure. A bake unit 5 is also provided which includes a hot plate 11 and a cool plate 12 respectively adapted to heat and cool the wafer before or after the photoresist coating or developing process. The spinner further includes a wide expose edge (WEE) unit 6 for exposing to light an unnecessary portion of the photoresist disposed on the peripheral edge portion of the wafer, and an interface 7 provided with a stocker interacting with an additional stepper 8 arranged adjacent to the WEE unit 6.
Although such a conventional installation may have a variable combination of processing units in accordance with processes to be carried out, it requires a relatively large installation area occupying a large portion of the entire semiconductor fabrication line because most processing units thereof are arranged in a planar manner, as shown in FIG. 1b or 1c.
For this reason, additions of processing units and new installations, involved due to an introduction of new processes and use of wafers increased in diameter, result in requirement of an increased installation area. This results in an increase in the area to be managed. Such an increase in the area to be managed results in an increase in manufacturing costs because the semiconductor fabrication line should essentially be in a super-clean environment. Furthermore, the entire fabrication line should be modified in design due to the introduction of new processes and the use of additional processing units or increased installation area caused by the use of enlarged wafers.
In order to solve such problems, a variety of techniques have been proposed. For example, a technique has been proposed in which a single feeding means is used to feed a workpiece (namely, a wafer) from a designated area to processing chambers. In accordance with this technique, a plurality of processing chambers are arranged in a multi-layered fashion around the feeding means in order to reduce the entire installation area.
Where this technique is applied to the fabrication of highly integrated semiconductor products of a 64 Mega grade or higher, requiring increased numbers of spin coaters, spin developers and bake units, it is inevitably necessary for those processing units to be arranged on three layers or more in order to achieve desired processes in each processing station using the single feeding means.
In the case of compact processing units such as bake units, a relatively easy multi-layered arrangement is achieved. However, where bulky processing units such as spin coaters or spin developers, which are important units for the processing of wafers, are arranged in a multi-layered fashion on three floors or more, the installation has a height of 3.5 m or more. For this reason, there is a great difficulty in the manufacture, repair, and maintenance of the installation. Furthermore, abnormal spaces are required on the semiconductor fabrication line which requires a super-clean state. For this reason, there is a problem in that the entire semiconductor fabrication line should be modified or newly designed.
Moreover, the single feeding means may be overloaded in the process of loading wafers into a plurality of processing chambers (at least 15 processing chambers) arranged in a multi-layered fashion around the feeding means or unloading wafers from those processing chambers. In this case, a degradation in the efficiency of the installation and a degradation in productivity may occur. In addition, there is a limitation in the space for occupying a variety of processing units required for the fabrication of semiconductor products with a super integration degree. Such a limited occupying space results in a great limitation in the use of processing units respectively required for achieving a variety of processes.